The invention pertains to semiconductor structures comprising silicon layers, as well as to semiconductor processing methods of forming silicon layers.
Silicon layers are a common constituent of semiconductor devices. Silicon layers can be utilized, for example, as interconnecting lines in integrated circuits, or as constituents of integrated circuit electrical components. Silicon layers are typically formed by chemical vapor deposition processes utilizing silane. Such processes can also utilize a dopant gas when it is desired to form an in situ doped silicon layer. Silicon layers can be deposited to comprise either essentially amorphous silicon, or essentially polycrystalline silicon. Essentially amorphous silicon is formed by depositing silicon at temperatures below 550xc2x0 C., while polysilicon is formed by depositing silicon at temperatures above 575xc2x0 C.
Generally, the essentially amorphous silicon is not 100% in an amorphous form, but rather comprises a small percentage of polycrystalline silicon. Also, the essentially polycrystalline silicon is not 100% in a polycrystalline form, but also comprises a small percentage of amorphous silicon. For purposes of interpreting this disclosure and the claims that follow, essentially amorphous silicon is defined as silicon which is 90 weight percent or more in an amorphous form, and essentially polycrystalline silicon is defined as silicon which is 90 weight percent or more in a polycrystalline form.
Frequently during semiconductor device fabrication, a layer of essentially polycrystalline silicon or essentially amorphous silicon is formed directly over and in contact with a different form of silicon. Such different form of silicon can comprise essentially amorphous silicon, essentially polycrystalline silicon, or monocrystalline silicon such as the silicon of a semiconductor wafer substrate. When a layer of essentially amorphous silicon or essentially polycrystalline silicon is formed over and in contact with a layer of a different type of silicon, a stress can occur between the layers. Such stress is undesired as it can lead to device failure in semiconductor circuits. Accordingly, it is desirable to develop alternate semiconductor fabrication methods which reduce stress between different silicon layers.
In another aspect of semiconductor processing, it is frequently desirable to create a dopant gradient within a semiconductive material. For instance, some fuses and resistors formed in monolithic integrated circuits preferably comprise a dopant gradient. It would be desirable to develop methods for providing dopant gradients in semiconductive materials.
In one aspect, the invention encompasses a semiconductor processing method wherein a silicon layer is deposited over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550xc2x0 C. to about 560xc2x0 C.
In another aspect, the invention encompasses a semiconductor processing method wherein a dopant gradient is formed in situ within a doped silicon layer during formation of the silicon layer in an uninterrupted deposition process. The uninterrupted deposition process includes, during the in situ doping, varying a temperature at which the doped silicon is formed.
In yet another aspect, the invention encompasses a semiconductor structure. The structure includes a silicon layer over a substrate. The silicon layer has a silicon inner portion, a silicon outer portion and a silicon transition region intermediate the silicon inner and outer portions. One of the inner and outer portions is essentially polycrystalline. The other of the inner and outer portions is essentially amorphous. The silicon transition region is neither essentially amorphous nor essentially polycrystalline and constitutes at least 1% of a thickness of the silicon layer.